1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to the structure of a thin film transistor (referred to as TFT hereinafter) as active element for high-density integrated circuits.
2. Description of the Prior Art
A MOS transistor of which channel region is of a semiconductor film formed over a substrate is called thin film transistor (TFT). TFT has being developed, for example, as switching matrix element for driving the liquid crystal display. Further with high-level integration of semiconductor device, TFT been becoming noticed because the overlay of a TFT on a transistor previously made at the surface of the semiconductor substrate enables high-level integration of semiconductor device. In particular, for SRAM, it is being in progress to use p-channel TFT as load element instead of conventional load element of polycrystalline silicon (referred to as polysilicon).
The TFT used in conventional semiconductor device has, for instance, such a structure that an insulating film is formed over the surface of a semiconductor substrate, a gate electrode is formed on the insulating film and coated with a gate-insulating film, a semiconductor film is deposited over the gate insulating film, and then source, drain, and channel regions are formed in the semiconductor film. A TFT like this made in such a way that the gate electrode underlies semiconductor film is called "bottom gate type TFT". On the other hand, a TFT where the gate electrode overlies the semiconductor film is called "top gate type TFT". In many cases the channel region is disposed parallel to the surface of the semiconductor substrate. The width and length of the channel is limited to the minimum processible size.
For the purpose of remitting the above-mentioned defect, for example, a TFT of the structure that the channel region made of a semiconductor film formed on the side face(s) of the gate electrode is reported in the 1984's Symposium on VLSI Technology, Digest of Technical Papers, pp. 8-9. It is of bottom gate type. The semiconductor device provided with the TFT is constructed as follows: At the surface of a p-type silicon substrate is made a n-channel MOS transistor which consists of n.sup.+ -type source and drain regions formed at the surface of the p-type silicon substrate, the first gate oxide film formed on the p-type silicon substrate, and a gate electrode formed on the first gate oxide film. The gate electrode is formed from n.sup.+ -type polysilicon.
The TFT is built over the n-channel MOS transistor, and the gate electrode of the latter is used as one common to both transistors. The second gate oxide film formed over the surfaces of the gate electrode, and n.sup.+ -type source and drain regions also constitutes the gate insulating film of the TFT. Over the second gate oxide film is formed a polysilicon film in which the p.sup.+ -type source and drain regions and the channel region of the TFT are formed by ion implantation of p-type impurity perpendicular to the silicon substrate. The channel region is formed on the opposite surface of the second gate oxide film to the side face of the gate electrode. The p.sup.+ -type source region is formed on the opposite surface of the second gate oxide film to the n.sup.+ -type source and drain regions. The p.sup.+ -type drain region is formed on the opposite surface of the second gate oxide film to the gate electrode. The surface of the channel region of the TFT is covered with a silicon oxide film used for side wall, and the remaining surface with silicon oxide film.
In this TFT, channel current flows perpendicularly to the surface of the silicon substrate. The channel length of the TFT depends substantially on the height (film thickness) of the gate electrode, and hence is possible to be smaller than the minimum processible size. The TFT therefore is capable of further size reduction. In the TFT of such structure however, though the channel length is short, the interface between the drain and channel regions is on the second gate oxide film because they are formed on the film. This reflects a great electric field at the drain region end which may be a cause of lowering the characteristics, for example, increasing in leak current.
A proposition for remitting this defect is made in Japanese Patent Laid-Open Application No. Hei. 2-30147. Over a silicon substrate is formed the first insulating film on which a TFT is made. The gate electrode of this TFT is made from polysilicon and formed on the first insulating film. A gate insulating film is formed on the side face of the gate electrode of the TFT, and the second insulating film as sufficiently thick as about 200 nm on the top. Besides a polysilicon film is formed to cover the gate insulating film and the first and second insulating films, and then subjected to ion implantation of p-type impurity perpendicularly to the silicon substrate, in the same way as in the aforesaid report, to form p.sup.+ -type source and drain regions, and channel region of the TFT. In the thus-obtained TFT, the p.sup.+ -type drain region is of offset structure with respect to the gate electrode because of the presence of the second insulating film, which brings a reduced electric field at the end of the p.sup.+ -type drain. This TFT therefore can contribute to improvement in characteristics over the TFT of the aforesaid report.
As an example of applying the TFT described in the aforesaid patent application to a high density integrated circuit, a p-type load element for SRAM is given below. The TFT in which polysilicon film is used as semiconductor film as described above, because of the channel region of polysilicon, is inferior in characteristics to the MOS transistor built at the surface of the single crystal silicon. Since polysilicon has a greater diffusion constant of impurity than single crystal silicon, characteristics of the TFT are poor if it is built to have a short channel length. For building p-channel TFT, ion implantation of B or BF.sub.2 is carried out to form source and drain regions. In this case if ion implantations for source and drain regions are carried out at a distance (referred to as implantation distance hereinafter) of up to 0.8 .mu.m, the off-current of the TFT increases because of the short channel effect. When the end part of the drain region is not of offset structure with respect to the gate electrode, the relationship of off-leak current per channel width to implantation distance along the channel are, assuming drain voltage=-3.3 V, 1 pA/.mu.m, to 0.8 .mu.m, and 10 to 100 pA/um to 0.7 .mu.m. Further 0.1 .mu.m shorter implantation distance causes two or more figures greater off-leak current. In brief, the implantation distances of up to 0.8 .mu.m has little offset-structure effect on off-leak current, and the turn-off will not be caused even at 0 V of gate voltage. On the other hand, at longer implantation distances the short channel effect becomes less, resulting in decrease of off-leak current. Off-leak current therefore tends to be smaller in the TFT having a drain region of off-set structure. Accordingly the TFT described in the aforesaid patent specification is considered to be little practical advantage as far as the actual characteristics are not remarkably improved. It can not meet strict requirement for off-leak current, which the p-type load element of SRAM makes.
Besides in the case, for example, of SRAM, where high-speed operation is required, for example, parasitic capacity is necessary to be as small as possible. In the TFT of the aforesaid report, the coupling capacities between n.sup.+ -type source and drain regions and p.sup.+ -type source region, and coupling capacity between the p.sup.+ -type drain region and the gate electrode are so great as to stand in the way of high-speed operation. In addition in the TFT described in the aforesaid patent specification, the gate electrode of it is used also as the gate electrode of the n-channel drive transistor in the SRAM, and not the first insulating film but the gate insulating film of the drive transistor is formed just beneath the p.sup.+ -type source region of the TFT, and in turn beneath it the source or drain region of the drive transistor is formed, so that the coupling capacity between these and the p.sup.+ -type source region of the TFT is great and stands in the way of high speed operation.